The present invention relates to a method for forming the device isolation structure of a semiconductor device, and more particularly, to a method for forming the device isolation structure of a semiconductor device which can prevent or at least minimize defects such as dislocation from occurring in a semiconductor substrate.
The trend in the development of semiconductor manufacturing technologies has been to develop the high speed operation and the high integration so that the semiconductor devices are rapidly and efficiently produced. It follows that this demand toward fine patterns and highly precise pattern dimensions will remain high and will likely gradually increase. This demand is applied not only to the patterns formed in device regions but also to device isolation structures which occupy a relatively large area.
In the conventional art, while a LOCOS (local oxidation of silicon) process has been used as a method for forming a device isolation structure, a bird's beak is likely to be formed on the edge of the upper end of the device isolation structure which is formed using the LOCOS fabrication process. Because of this fact, the LOCOS fabrication process exhibit undesirable drawbacks such as limiting the size reduction of an active region.
In a STI (shallow trench isolation) process, a device isolation structure can be formed while preventing the formation of a bird's beak, and therefore, the size of an active region can be secured, whereby a highly integrated semiconductor device can be realized. Due to this fact, the STI process is currently adopted in most semiconductor devices.
The STI process is implemented in a manner such that a device isolation region of a semiconductor substrate is etched to form a trench and an insulation layer is filled in a trench.
In the STI process, in general, a SiO2 layer or an O3-TEOS (tetra ethyl ortho silicate) layer is used as an insulation layer for filling a trench. The insulation layer is filled in a trench through CVD (chemical vapor deposition) or HDP-CVD (high density plasma-chemical vapor deposition).
Meanwhile, as semiconductor devices trend toward high integration, the aspect ratio of a trench increases. In this regard, in the case of a semiconductor device having a sub-100 nm level, a method has been proposed, in which a PSZ (polysilazane) layer as a flowable insulation layer is used as an insulation layer for filling a trench.
Hereafter, a conventional method for forming the device isolation structure of a semiconductor device, in which a PSZ layer is used as an insulation layer for filling a trench, will be schematically described.
After a pad oxide layer and a pad nitride layer are sequentially formed on a semiconductor substrate, the pad nitride layer is patterned. The pad oxide layer and the semiconductor substrate are etched using the patterned pad nitride layer as a hard mask, and as a result, a trench is formed in the semiconductor substrate. Then, after a sidewall oxide, a linear nitride layer and a linear oxide layer are sequentially formed on the semiconductor substrate including a trench, perhydro-polysilazane is coated through an SOD (spin-on dielectric) process to fill a trench.
The perhydro-polysilazane is baked and the solvent contained in the perhydro-polysilazane volatilizes, by which a PSZ layer is formed. Next, the PSZ layer is annealed and is thereby converted into a SiO2 layer. The SiO2 layer is then densified. The densified SiO2 layer is CMPed (chemically and mechanically polished) until the pad nitride layer is exposed. The exposed pad nitride layer and the pad oxide layer are sequentially removed, as a result of which a trench type device isolation structure is formed.
FIG. 1 is a diagrammatic view explaining a baking and annealing procedure in the formation of the device isolation structure of a semiconductor device according to the conventional art.
Referring to FIG. 1, after the semiconductor substrate, on which the perhydro-polysilazane is filled in a trench, is loaded into a process chamber, the perhydro-polysilazane is baked at a temperature of 150° C., for example, 150˜200° C., for 3 minutes. The solvent contained in the perhydro-polysilazane volatilizes by the baking, and as a result, the PSZ layer is formed.
The PSZ layer is first annealed at a temperature of 300˜400° C. for about 60 minutes. The first annealing is implemented as wet annealing in the atmosphere containing water vapor (H2O). The PSZ layer, which is constituted by the solute of the perhydro-polysilazane ((SiH2NH)n where n=a positive integer), is converted into the SiO2 layer by the first annealing.
The SiO2 layer is second annealed at a relatively high temperature of 750˜900° C. The second annealing is also implemented as wet annealing in the atmosphere containing water vapor (H2O). The SiO2 layer is densified by the second annealing. Then, the semiconductor substrate is unloaded from the process chamber.
However, in the conventional art as described above, after the first annealing is implemented, a temperature abruptly rises in the second annealing which is implemented at the relatively high temperature. Due to an abrupt rise in temperature, the semiconductor substrate excessively shrinks in volume.
FIG. 2 is the photograph of a semiconductor device, illustrating the defects occurring in the conventional art.
If the volume of a semiconductor substrate excessively shrinks, stress is induced in the semiconductor substrate. As a result, as can be seen from FIG. 2, defects such as dislocation occur in the active region of the semiconductor substrate due to the stress. Also, if the defects occur in the active region of the semiconductor substrate, the characteristics of a semiconductor device are degraded, and the manufacturing yield of the semiconductor device decreases.
Meanwhile, a method for preventing an abrupt temperature rise during annealing of a PSZ layer has been disclosed in Korean Patent No. 0574731. In this method, after a PSZ layer is annealed at a low temperature and converted into a SiO2 layer, the converted SiO2 layer is CMPed and then annealing is implemented at a high temperature.
Nevertheless, in this case, while the annealing is implemented at a high temperature, because oxygen or moisture leaks into a linear nitride layer which is partially lost by CMP and thereby the active regions of a semiconductor device are partially oxidated, GOI (gate oxide integrity) is degraded. Thus, it is difficult to actually apply the method to a process for manufacturing a semiconductor device.